View SST49LF008A-33-4C-EIE_684248.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

?2006 silicon storage technology, inc. s71161-11-000 3/06 1 the sst logo and superflash are registered trademarks of silicon storage technology, inc. intel is a registered trademark of intel corporation. these specifications are subject to change without notice. data sheet features: ? firmware hub for intel 8xx chipsets ? 8 mbit superflash memory array for code/data storage ? 1024k x8 ? flexible erase capability ? uniform 4 kbyte sectors ? uniform 64 kbyte overlay blocks ? 64 kbyte top boot block protection ? chip-erase for pp mode only ? single 3.0-3.6v read and write operations ? superior reliability ? endurance:100,000 cycles (typical) ? greater than 100 years data retention ? low power consumption ? active read current: 6 ma (typical) ? standby current: 10 a (typical) ? fast sector-erase/byte-program operation ? sector-erase time: 18 ms (typical) ? block-erase time: 18 ms (typical) ? chip-erase time: 70 ms (typical) ? byte-program time: 14 s (typical) ? chip rewrite time: 15 seconds (typical) ? single-pulse program or erase ? internal timing generation ? two operational modes ? firmware hub interface (fwh) mode for in-system operation ? parallel programming (pp) mode for fast production programming ? firmware hub hardware interface mode ? 5-signal communication interface supporting byte read and write ? 33 mhz clock frequency operation ? wp# and tbl# pins provide hardware write protect for entire chip and/or top boot block ? block locking register for all blocks ? standard sdp command set ? data# polling and toggle bit for end-of-write detection ? 5 gpi pins for system design flexibility ? 4 id pins for multi-chip selection ? parallel programming (pp) mode ? 11-pin multiplexed address and 8-pin data i/o interface ? supports fast in-system or prom programming for manufacturing ? cmos and pci i/o compatibility ? packages available ? 32-lead plcc ? 32-lead tsop (8mm x 14mm) ? 40-lead tsop (10mm x 20mm) ? non-pb (lead-free) packages available ? all non-pb (lead-free) devices are rohs compliant product description the sst49lf008a flash memory devices are designed to be read-compatible with the intel 82802 firmware hub (fwh) device for pc-bios application. these devices pro- vide protection for the storage and update of code and data in addition to addin g system design flex ibility through five general purpose inputs. two interface modes are sup- ported by the sst49lf008a: firmware hub (fwh) inter- face mode for in-system programming and parallel programming (pp) mode for fast factory programming of pc-bios applications. the sst49lf008a flash memory devices are manufac- tured with sst?s proprietary, high performance superflash technology. the split-gate cell design and thick-oxide tun- neling injector atta in better reliability and manufacturability compared with alternate approaches. the sst49lf008a devices significantly improve performance and reliability, while lowering power consumption. the sst49lf008a devices write (program or erase) with a single 3.0-3.6v power supply. they use less energy dur- ing erase and program than alternative flash memory tech- nologies. the total energy consumed is a function of the applied voltage, current and time of application. since for any given voltage range, the superflash technology uses less current to program and has a shorter erase time, the total energy consumed during any erase or program oper- ation is less than alternative flash memory technologies. the sst49lf008a products provide a maximum byte- program time of 20 sec. the entire memory can be erased and programmed byte-by-byte typically in 15 sec- onds when using status detection features such as toggle bit or data# polling to indicate the completion of program operation. the superflash technology provides fixed erase and program times independent of the number of erase/ program cycles performed. therefore the system software 8 mbit firmware hub sst49lf008a sst49lf008a8 mb firmware hub for intel 8xx chipsets
2 data sheet 8 mbit firmware hub sst49lf008a ?2006 silicon storage technology, inc. s71161-11-000 3/06 or hardware does not have to be calibrated or correlated to the cumulated number of erase/program cycles as is nec- essary with alternative flash memory technologies, whose erase and program time increase with accumulated erase/ program cycles. to protect against inadvertent write, the sst49lf008a devices employ hardware and software data (sdp) protec- tion schemes. it is offered with typical endurance of 100,000 cycles. data retention is rated at greater than 100 years. to meet high density, surface mount requirements, the sst49lf008a devices are offered in a 32-lead tsop package. in addition, the sst49lf008a is offered in 32- lead plcc and 40-lead tsop pac kages. see figures 2, 3, and 4 for pin assignments and table 1 for pin descriptions. table of contents product description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 list of figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 list of tables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 device memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 design considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 product identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 firmware hub (fwh) mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 device operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 firmware hub interface cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 abort mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 response to invalid fields. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 device memory hardware write protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 write operation status detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 data# polling (dq 7 ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 toggle bit (dq 6 ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 multiple device selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 general purpose inputs register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 block locking registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 write lock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 lock down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 jedec id registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
data sheet 8 mbit firmware hub sst49lf008a 3 ?2006 silicon storage technology, inc. s71161-11-000 3/06 parallel programming mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 device operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 byte-program operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 sector-erase operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 block-erase operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 chip-erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 write operation status detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 data protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 software command sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 ac characteristics (fwh mode). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 ac characteristics (pp mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 product ordering information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 packaging diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
4 data sheet 8 mbit firmware hub sst49lf008a ?2006 silicon storage technology, inc. s71161-11-000 3/06 list of figures figure 1: functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 2: pin assignments for 32-lead tsop (8mm x 14mm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 3: pin assignments for 32-lead plcc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 4: pin assignments for 40-lead tsop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 5: device memory map for sst49lf008a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 0 figure 6: single-byte read waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 7: write waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 8: clk waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 9: reset timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 10: output timing parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 11: input timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 12: reset timing diagram (pp mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 13: read cycle timing diagram (pp mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 14: write cycle timing diagram (pp mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 15: data# polling timing dia gram (pp mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 16: toggle bit timing diagram (pp mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 17: byte-program timing diagram (pp mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 18: sector-erase timing diagram (pp mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1 figure 19: block-erase timing diagram (pp mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 20: chip-erase timing diagram (pp mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 21: software id entry and read (pp mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 22: software id exit and reset (pp mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 23: ac input/output reference waveforms (pp mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 24: a test load example (pp mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 25: byte-program algorithm. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 26: wait options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 figure 27: software product command flowcharts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6 figure 28: erase command sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 figure 29: 32-lead plastic lead chip carrier (plcc) sst package code: nh . . . . . . . . . . . . . . . . . . . . 39 figure 30: 32-lead thin small outline package (tsop) 8mm x 14mm sst package code: wh . . . . . . 40 figure 31: 40-lead thin small outline package (tsop) 10mm x 20mm sst package code: ei . . . . . . 41
data sheet 8 mbit firmware hub sst49lf008a 5 ?2006 silicon storage technology, inc. s71161-11-000 3/06 list of tables table 1: pin description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 2: product identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 3: fwh read cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 4: fwh write cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 5: general purpose inputs register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 6: block locking registers for sst49lf008a. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 6 table 7: block locking register bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 8: operation modes selection (pp mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 9: software command sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 10: dc operating characteristics (all interfaces) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 11: recommended system power-up timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 12: pin impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 13: reliability characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 14: clock timing parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 15: read/write cycle timing parameters, v dd =3.0-3.6v (fwh mode) . . . . . . . . . . . . . . . . . . . . 24 table 16: ac input/output specifications, v dd =3.0-3.6v (fwh mode) . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 17: reset timing parameters, v dd =3.0-3.6v (fwh mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 18: interface measurement condition parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 19: read cycle timing parameters, v dd =3.0-3.6v (pp mode) . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 20: program/erase cycle timing parameters, v dd =3.0-3.6v (pp mode) . . . . . . . . . . . . . . . . . . 27 table 21: reset timing parameters, v dd =3.0-3.6v (pp mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 22: revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
6 data sheet 8 mbit firmware hub sst49lf008a ?2006 silicon storage technology, inc. s71161-11-000 3/06 functional block diagram figure 1: functional block diagram 1161 b1.2 y-decoder i/o buffers and data latches address buffers & latches x-decoder superflash memory control logic clk rst# ic fgpi[4:0] programmer interface wp# tbl# init# id[3:0] fwh4 r/c# oe# we# a[10:0] dq[7:0] fwh[3:0] fwh interface
data sheet 8 mbit firmware hub sst49lf008a 7 ?2006 silicon storage technology, inc. s71161-11-000 3/06 pin assignments figure 2: pin assignments for 32-lead tsop (8mm x 14mm) figure 3: pin assignments for 32-lead plcc nc nc nc v ss (v ss ) ic (ic) a10 (fgpi4) r/c# (clk) v dd (v dd ) nc rst# (rst#) a9 (fgpi3) a8 (fgpi2) a7 (fgpi1) a6 (fgpi0) a5 (wp#) a4 (tbl#) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 oe# (init#) we# (fwh4) v dd (v dd ) dq7 (res) dq6 (res) dq5 (res) dq4 (res) dq3 (fwh3) v ss (v ss ) dq2 (fwh2) dq1 (fwh1) dq0 (fwh0) a0 (id0) a1 (id1) a2 (id2) a3 (id3) 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 1161 32-tsop p1.0 standard pinout top view die up ( ) designates fwh mode 5 6 7 8 9 10 11 12 13 29 28 27 26 25 24 23 22 21 a7(fgpi1) a6 (fgpi0) a5 (wp#) a4 (tbl#) a3 (id3) a2 (id2) a1 (id1) a0 (id0) dq0 (fwh0) ic (ic) v ss (v ss ) nc nc v dd (v dd ) oe# (init#) we# (fwh4) nc dq7 (res) 4 3 2 1 32 31 30 a8 (fgpi2) a9 (fgpi3) rst# (rst#) nc v dd (v dd ) r/c# (clk) a10 (fgpi4) 32-lead plcc top view 1161 32-plcc p2.3 14 15 16 17 18 19 20 dq1 (fwh1) dq2 (fwh2) v ss (v ss ) dq3 (fwh3) dq4 (res) dq5 (res) dq6 (res) ( ) designates fwh mode
8 data sheet 8 mbit firmware hub sst49lf008a ?2006 silicon storage technology, inc. s71161-11-000 3/06 figure 4: pin assignments for 40-lead tsop 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 1232 40-tsop p1.0 standard pinout top view die up nc (nc) ic (ic) nc (nc) nc (nc) nc (nc) nc (nc) a10 (fgpi4) nc (nc) r/c# (clk) v dd nc (nc) rst# (rst#) nc (nc) nc (nc) a9 (fgpi3) a8 (fgpi2) a7 (fgpi1) a6 (fgpi0) a5 (wp#) a4 (tbl#) v ss v dd (fwh4) we# (init#) oe# (nc) nc (res) dq7 (res) dq6 (res) dq5 (res) dq4 (nc) nc v ss v ss (fwh3) dq3 (fwh2) dq2 (fwh1) dq1 (fwh0) dq0 (id0) a0 (id1) a1 (id2) a2 (id3) a3 ( ) designates fwh mode
data sheet 8 mbit firmware hub sst49lf008a 9 ?2006 silicon storage technology, inc. s71161-11-000 3/06 table 1: pin description symbol pin name type 1 interface functions pp fwh a 10 -a 0 address i x inputs for low-order addresses during read and write operations. addresses are internally latched during a write cycle. for the pro- gramming interface, these addresses are latched by r/c# and share the same pins as the high-order address inputs. dq 7 -dq 0 data i/o x to output data during read cycles and receive input data during write cycles. data is internally la tched during a write cycle. the out- puts are in tri-state when oe# is high. oe# output enable i x to gate the data output buffers we# write enable i x to control the write operations ic interface configuration pin i x x this pin determines which interface is operational. when held high, programmer mode is enabled and when held low, fwh mode is enabled. this pin must be setup at power-up or before return from reset and not change during device operation. this pin is internally pulled- down with a resistor between 20-100 k . init# initialize i x this is the second reset pin for in-system use. this pin is internally combined with the rst# pin; if this pin or rst# pin is driven low, identical operation is exhibited. id[3:0] identification inputs i x these four pins are part of the mechanism that allows multiple parts to be attached to the same bus. the strapping of these pins is used to identify the component.the boot device must have id[3:0]=0000 and it is recommended that all subsequent devices should use sequential up-count strappi ng. these pins are internally pulled-down with a resistor between 20-100 k . fgpi[4:0] general purpose inputs i x these individual inputs can be used for additional board flexib ility. the state of these pins can be read through gpi_reg register. these inputs should be at their desired state before the start of the pci clock cycle during which the read is attempted, and should remain in place until the end of the read cycle. unused gpi pins must not be floated. tbl# top block lock i x when low, prevents programming to the boot block sectors at top of memory. when tbl# is high it disables hardware write protection for the top block sectors. this pi n cannot be left unconnected. fwh[3:0] fwh i/os i/o x i/o communications clk clock i x to provide a clock input to the control unit fwh4 fwh input i x input communications rst# reset i x x to reset the operation of the device wp# write protect i x when low, prevents programming to all but the highest addressable blocks. when wp# is high it disables hardware write protection for these blocks. this pin cannot be left unconnected. r/c# row/column select i x select for the programming interface, this pin determines whether the address pins are pointing to the row addresses, or to the column addresses. res reserved x these pins must be left unconnected. v dd power supply pwr x x to provide power supply (3.0-3.6v) v ss ground pwr x x circuit ground (ov reference) all v ss pins must be grounded. nc no connection i x x unconnected pins t1.4 1161 1. i = input, o = output
10 data sheet 8 mbit firmware hub sst49lf008a ?2006 silicon storage technology, inc. s71161-11-000 3/06 device memory map figure 5: device memory map for sst49lf008a 0fffffh 0f0000h 0effffh 0e0000h 0dffffh 0d0000h 0cffffh 0c0000h 0bffffh 0b0000h 0affffh 0a0000h 09ffffh 090000h 08ffffh 080000h 07ffffh 070000h 06ffffh 060000h 05ffffh 050000h 04ffffh 040000h 03ffffh 030000h 02ffffh 020000h 01ffffh 010000h 00ffffh block 7 block 8 block 6 block 5 block 4 block 3 block 2 block 1 block 15 block 14 block 13 block 12 block 11 block 10 block 9 block 0 (64 kbyte) 1161 f08.0 wp# for block 0~14 tbl# 4 kbyte sector 1 4 kbyte sector 2 4 kbyte sector 15 4 kbyte sector 0 boot block 002000h 001000h 000000h
data sheet 8 mbit firmware hub sst49lf008a 11 ?2006 silicon storage technology, inc. s71161-11-000 3/06 design considerations sst recommends a high frequency 0.1 f ceramic capacitor to be placed as close as possible between v dd and v ss less than 1 cm away from the v dd pin of the device. additionally, a low frequency 4.7 f electrolytic capacitor from v dd to v ss should be placed within 1 cm of the v dd pin. if you use a socket for programming purposes add an additional 1-10 f next to each socket. the rst# pin must remain stable at v ih for the entire dura- tion of an erase operation. wp# must remain stable at v ih for the entire duration of the erase and program operations for non-boot block sectors. to write data to the top boot block sectors, the tbl# pin must also remain stable at v ih for the entire duration of the erase and program operations. product identification the product identification mode identifies the device as the sst49lf008a and manufacturer as sst. mode selection the sst49lf008a flash memory devices can operate in two distinct interface modes: the firmware hub interface (fwh) mode and the parallel programming (pp) mode. the ic (interface configuration pin) is used to set the interface mode selection. if the ic pin is set to logic high, the device is in pp mode; while if the ic pin is set low, the device is in the fwh mode. the ic selection pin must be configured prior to device operation. the ic pin is internally pulled down if the pin is not connected. in fwh mode, the device is configured to interface with its host using intel?s firmware hub proprietary protocol. commu- nication between host and the sst49lf008a occurs via the 4-bit i/o communication signals, fwh [3:0] and the fwh4. in pp mode, the device is programmed via an 11- bit address and an 8-bit data i/o parallel signals. the address inputs are multiplexed in row and column selected by control signal r/c# pin. the column addresses are mapped to the higher internal addresses, and the row addresses are mapped to the lower internal addresses. see the device memory map in figure 5 for address assignments. firmware hub (fwh) mode device operation the fwh mode uses a 5-signal communication interface, fwh[3:0] and fwh4, to control operations of the sst49lf008a. operations such as memory read and memory write uses intel fwh propriety protocol. jedec standard sdp (software data protection) byte-program, sector-erase and block-erase command sequences are incorporated into the fwh memory cycles. chip-erase is only available in pp mode. the device enters standby mode when fwh4 is high and no internal operation is in progress. the device is in ready mode when fwh4 is low and no activity is on the fwh bus. firmware hub interface cycles addresses and data are transferred to and from the sst49lf008a by a series of ?fields,? where each field con- tains 4 bits of data. sst49lf008a supports only single- byte read and write, and all fields are one clock cycle in length. field sequences and cont ents are strictly defined for read and write operations. addresses in this section refer to addresses as seen from the sst49lf008a?s ?point of view,? some calculation will be required to translate these to the actual locations in the memory map (and vice versa) if multiple memory devices are used on the bus. tables 3 and 4 list the field sequences for read and write cycles. table 2: product identification byte data jedec id address location manufacturer?s id 0000h bfh ffbc0000h device id sst49lf008a 0001h 5ah ffbc0001h t2.7 1161
12 data sheet 8 mbit firmware hub sst49lf008a ?2006 silicon storage technology, inc. s71161-11-000 3/06 figure 6: single-byte read waveforms table 3: fwh read cycle clock cycle field name field contents fwh[3:0] 1 fwh[3:0] direction comments 1 start 1101 in fwh4 must be active (low) for the part to respond. only the last start field (before fwh4 transitions high) should be rec- ognized. the start field contents indicate a fwh memory read cycle. 2 idsel 0000 to 1111 in indicates which fwh device s hould respond. if the to idsel (id select) field matches the value id[3 :0], then that particular device will respond to the whole bus cycle. 3-9 imaddr yyyy in these seven clock cyc les make up the 28-bit memory address. yyyy is one nibble of the entire address. addresses are transferred most-significant nibble first. 10 imsize 0000 (1 byte) in a field of this size indicates how many bytes will be or trans- ferred during multi-byte operations. the sst49lf008a will only support single-byte operation. imsize=0000b 11 tar0 1111 in then float in this clock cycle, the master (intel ich) has driven the bus then float to all ?1?s and then floats the bus, prior to the next clock cycle. this is the first part of the bus ?turnaround cycle.? 12 tar1 1111 (float) float then out the sst49lf008a takes control of the bus during this cycle. during the next clock cycle, it will be driving ?sync data.? 13 rsync 0000 (ready) out during this clock cycle, the fwh will generate a ?ready- sync? (rsync) indicating that the least-significant nibble of the least-significant byte will be available during the next clock cycle. 14 data yyyy out yyyy is the least-significant nibble of the least-significant data byte. 15 data yyyy out yyyy is the most-significa nt nibble of the least-significant data byte. 16 tar0 1111 out then float in this clock cycle, the sst 49lf008a has driven the bus to all ones and then floats the bus prior to the next clock cycle. this is the first part of the bus ?turnaround cycle.? 17 tar1 1111 (float) float then in the master (intel ich) resumes control of the bus during this cycle. t3.3 1161 1. field contents are valid on the ri sing edge of the present clock cycle. clk fwh4 fwh[3:0] 1161 f09.0 str tar rsync ims imaddr ids data ta r
data sheet 8 mbit firmware hub sst49lf008a 13 ?2006 silicon storage technology, inc. s71161-11-000 3/06 figure 7: write waveforms table 4: fwh write cycle clock cycle field name field contents fwh[3:0] 1 fwh[3:0] direction comments 1 start 1110 in fwh4 must be active (low) for the part to respond. only the last start field ( before fwh4 transitions high) should be recognized. the start field contents indi- cate a fwh memory read cycle. 2 idsel 0000 to 1111 in indicates which sst49lf008a device should respond. if the idsel (id select) field matches the value id[3:0], then that particular device will respond to the whole bus cycle. 3-9 imaddr yyyy in these seven clock cycles make up the 28-bit memory address. yyyy is one nibble of the entire address. addresses are transferred most-significant nibble first. 10 imsize 0000 (1 byte) in this size field indicates how many bytes will be transferred during multi-byte operations. the fwh only supports single-byte writes. imsize=0000b 11 data yyyy in this field is the least-si gnificant nibble of the data byte. this data is either the data to be programmed into the flash memory or any valid flash command. 12 data yyyy in this field is the most-significant nibble of the data byte. 13 tar0 1111 in then float in this clock cycle, the master (intel ich) has driven the then float bus to all ?1?s and then floats the bus prior to the next clock cycle. this is the first part of the bus ?turnaround cycle.? 14 tar1 1111 (float) float then out the sst49lf008a takes control of the bus during this cycle. during the next clock cycle it will be driving the ?sync? data. 15 rsync 0000 out the sst49lf008a outputs the values 0000, indicating that it has received data or a flash command. 16 tar0 1111 out then float in this clock cycle, the sst49lf008a has driven the bus to all then float ?1?s and then floats the bus prior to the next clock cycle. this is the first part of the bus ?turnaround cycle.? 17 tar1 1111 (float) float then in the master (intel ich) resumes control of the bus during this cycle. t4.4 1161 1. field contents are valid on the ri sing edge of the present clock cycle. clk fwh4 fwh[3:0] 1161 f10.0 str data ta r ta r rsync ims imaddr ids
14 data sheet 8 mbit firmware hub sst49lf008a ?2006 silicon storage technology, inc. s71161-11-000 3/06 abort mechanism if fwh4 is driven low for one or more clock cycles during a fwh cycle, the cycle will be terminated and the device will wait for the abort command. the host may drive the fwh[3:0] with ?1111b? (abort command) to return the device to ready mode. if abort occurs during a write oper- ation, the data may be incorrectly altered. response to invalid fields during fwh operations, the fwh will not explicitly indicate that it has received invalid field sequences. the response to specific invalid fields or sequences is as follows: address out of range: the fwh address sequence is 7 fields long (28 bits), but only the last five address fields (20 bits) will be dec oded by sst49lf008a. address a 22 has the special function of directing reads and writes to the flash core (a 22 =1) or to the register space (a 22 =0). invalid imsize field: if the fwh receives an invalid size field during a read or write oper ation, the devi ce will reset and no operation will be attemp ted. the sst49lf008a will not generate any kind of response in this situation. invalid- size fields for a read/write cycle are anything but 0000b. device memory hardware write protection the top boot lock (tbl#) and write protect (wp#) pins are provided for hardware write protection of device memory in the sst49lf008a. the tbl# pin is used to write protect 16 boot sectors (64 kbyte) at the highest flash memory address range for the sst49lf008a. wp# pin write protects the remaining sectors in the flash memory. an active low signal at the tbl# pin prevents program and erase operations of the top boot sectors. when tbl# pin is held high, write protection of the top boot sectors is then determined by the boot block locking register. the wp# pin serves the same function for the remaining sectors of the device memory. the tbl# and wp# pins write protec- tion functions operate independently of one another. both tbl# and wp# pins must be set to their required protection states prior to starting a program or erase operation. a logic level change occurring at the tbl# or wp# pin during a program or erase operation could cause unpredictable results. tbl# and wp# pins cannot be left unconnected. tbl# is internally or?ed with the top boot block locking register. when tbl# is low, the top boot block is hard- ware write protected regardless of the state of the write- lock bit for the boot block locking register. clearing the write-protect bit in the register when tbl# is low will have no functional effect, even though the register may indicate that the block is no longer locked. wp# is internally or?ed with the block locking register. when wp# is low, the blocks are hardware write pro- tected regardless of the state of the write-lock bit for the corresponding block locking registers. clearing the write-protect bit in any register when wp# is low will have no functional effect, even though the register may indicate that the block is no longer locked. reset a v il on init# or rst# pin initiates a device reset. init# and rst# pins have the same function internally. it is required to drive init# or rst# pins low during a system reset to ensure proper cpu initialization. during a read operation, driving init# or rst# pins low deselects the device and places the output drivers, fwh[3:0], in a high-impedance state. the reset signal must be held low for a minimal duration of time t rstp. a reset latency will occur if a reset procedure is performed during a program or erase operation. see table 17, reset timing parameters for more information. a device reset during an active program or erase will abort the operation and memory contents may become invalid due to data being altered or corrupted from an incomplete erase or program operation. write operation status detection the sst49lf008a device provides two software means to detect the completion of a write (program or erase) cycle, in order to optimize the system write cycle time. the soft- ware detection includes two status bits: data# polling (dq 7 ) and toggle bit (dq 6 ). the end-of-write detection mode is incorporated into the fwh read cycle. the actual completion of the nonvolatile write is asynchronous with the system; therefore, either a data# polling or toggle bit read may be simultaneous with the completion of the write cycle. if this occurs, the system may possibly get an errone- ous result, i.e., valid data may appear to conflict with either dq 7 or dq 6 . in order to prevent spurious rejection, if an erroneous result occurs, the software routine should include a loop to read the accessed location an additional two (2) times. if both reads are valid, then the device has completed the write cycle, otherwise the rejection is valid.
data sheet 8 mbit firmware hub sst49lf008a 15 ?2006 silicon storage technology, inc. s71161-11-000 3/06 data# polling (dq 7 ) when the sst49lf008a device is in the internal program operation, any attempt to read dq 7 will produce the com- plement of the true data. once the program operation is completed, dq 7 will produce true data. note that even though dq 7 may have valid data immediately following the completion of an internal write operation, the remaining data outputs may still be invalid: valid data on the entire data bus will appear in subsequent successive read cycles after an interval of 1 s. during internal erase opera- tion, any attempt to read dq 7 will produce a ?0?. once the internal erase operation is completed, dq 7 will produce a ?1?. proper status will not be given using data# polling if the address is in the invalid range. toggle bit (dq 6 ) during the internal program or erase operation, any con- secutive attempts to read dq 6 will produce alternating ?0?s and ?1?s, i.e., toggling between 0 and 1. when the internal program or erase operation is completed, the toggling will stop. multiple device selection the four id pins, id[3:0], allow multiple devices to be attached to the same bus by using different id strapping in a system. when the sst49lf008a is used as a boot device, id[3:0] must be strapped as 0000, all subsequent devices should use a sequential up-count strapping (i.e. 0001, 0010, 0011, etc.). t he sst49lf008a will compare the strapping values, if there is a mismatch, the device will ignore the remainder of the cycle and go into standby mode. for further information regarding fwh device map- ping and paging, please refer to the intel 82801(ich) i/o controller hub documentation. since there is no id support in pp mode, to program multiple devices a stand-alone prom programmer is recommended. registers there are three types of registers available on the sst49lf008a, the general purpose inputs register, block locking registers and the jedec id registers. these regis- ters appear at their respective address location in the 4 gbyte system memory map. unused register locations will read as 00h. attempts to read or write to any registers dur- ing internal write operations will be ignored. general purpose inputs register the gpi_reg (general purpose inputs register) passes the state of fgpi[4:0] pins at power-up on the sst49lf008a. it is recommended that the fgpi[4:0] pins are in the desired state before fwh4 is brought low for the beginning of the bus cycle, and remain in that state until the end of the cycle. there is no default value since this is a pass-through register. the gpi register for the boot device appears at ffbc0100h in the 4 gbyte system memory map, and will appear elsewhere if the device is not the boot device. register is not available for read when the device is in erase/program operation. see table 5 for the gpi_reg bits and function. block locking registers sst49lf008a provides software controlled lock pro- tection through a set of block locking registers. the block locking registers are read/write registers and it is accessible through standard addressable memory locations specified in table 6. unused register loca- tions will read as 00h. table 5: general purpose inputs register bit function pin # 32-plcc 32-tsop 40-tsop 7:5 reserved - - - 4 fgpi[4] reads status of general purpose input pin 30 6 7 3 fgpi[3] reads status of general purpose input pin 31115 2 fgpi[2] reads status of general purpose input pin 41216 1 fgpi[1] reads status of general purpose input pin 51317 0 fgpi[0] reads status of general purpose input pin 61418 t5.3 1161
16 data sheet 8 mbit firmware hub sst49lf008a ?2006 silicon storage technology, inc. s71161-11-000 3/06 table 6: block locking registers for sst49lf008a 1 register block size protected memory address range memory map register address t_block_lk 64k 0fffffh - 0f0000h ffbf0002h t_minus01_lk 64k 0effffh - 0e0000h ffbe0002h t_minus02_lk 64k 0dffffh - 0d0000h ffbd0002h t_minus03_lk 64k 0cffffh - 0c0000h ffbc0002h t_minus04_lk 64k 0bffffh - 0b0000h ffbb0002h t_minus05_lk 64k 0affffh - 0a0000h ffba0002h t_minus06_lk 64k 09ffffh - 090000h ffb90002h t_minus07_lk 64k 08ffffh - 080000h ffb80002h t_minus08_lk 64k 07ffffh - 070000h ffb70002h t_minus09_lk 64k 06ffffh - 060000h ffb60002h t_minus10_lk 64k 05ffffh - 050000h ffb50002h t_minus11_lk 64k 04ffffh - 040000h ffb40002h t_minus12_lk 64k 03ffffh - 030000h ffb30002h t_minus13_lk 64k 02ffffh - 020000h ffb20002h t_minus14_lk 64k 01ffffh -010000h ffb10002h t_minus15_lk 64k 00ffffh - 000000h ffb00002h t6.4 1161 1. default value at power up is 01h table 7: block locking register bits reserved bit [7..2] lock-down bit [1] write-lock bit [0] lock status 000000 0 0 full access 000000 0 1 write locked (default state at power-up) 000000 1 0 locked open (full access locked down) 000000 1 1 write locked down t7.3 1161
data sheet 8 mbit firmware hub sst49lf008a 17 ?2006 silicon storage technology, inc. s71161-11-000 3/06 write lock the write-lock bit, bit 0, controls the lock state described in table 7. the default write status of all blocks after power- up is write locked. when bit 0 of the block locking register is set, program and erase operations for the corresponding block are prevented. clearing the write-lock bit will unpro- tect the block. the write-lock bit must be cleared prior to starting a program or erase operation since it is sampled at the beginning of the operation. the write-lock bit functions in conjunction with the hard- ware write lock pin tbl# for the top boot block. when tbl# is low, it overrides the software locking scheme. the top boot block locking register does not indicate the state of the tbl# pin. the write-lock bit functions in conjunction with the hard- ware wp# pin for blocks 0 to 6. when wp# is low, it over- rides the software locking scheme. the block locking register does not indicate the state of the wp# pin. lock down the lock-down bit, bit 1, controls the block locking regis- ter as described in table 7. when in the fwh interface mode, the default lock down status of all blocks upon power-up is not locked down. once the lock-down bit is set, any future attempted changes to that block locking register will be i gnored. the lock-down bit is only cleared upon a device reset with rst# or init# or power down. current lock down status of a particular block can be determined by reading the corresponding lock-down bit. once a block?s lock-down bit is set, the write-lock bits for that block can no longer be modified, and the block is locked down in its current state of write accessibility. jedec id registers the jedec id registers for the boot device appear at ffbc0000h and ffbc0001h in the 4 gbyte system memory map, and will appear el sewhere if the device is not the boot device. register is not available for read when the device is in erase/program operation. unused register location will read as 00h. refe r to the relevant application note for details. see table 2 for the device id code. parallel programming mode device operation commands are used to initiate the memory operation func- tions of the device. the data portion of the software com- mand sequence is latched on the rising edge of we#. during the software command sequence the row address is latched on the falling edge of r/c# and the column address is latched on the rising edge of r/c#. reset a v il on rst# pin initiates a device reset. read the read operation of the sst49lf008a device is con- trolled by oe#. oe# is the output control and is used to gate data from the output pins. refer to the read cycle timing diagram, figure 13, for further details. byte-program operation the sst49lf008a device is programmed on a byte-by- byte basis. before programming, one must ensure that the sector, in which the byte which is being programmed exists, is fully erased. the byte-program operation is initiated by executing a four-byte command load sequence for soft- ware data protection with address (ba) and data in the last byte sequence. during the byte-program operation, the row address (a 10 -a 0 ) is latched on the falling edge of r/c# and the column address (a 21 -a 11 ) is latched on the rising edge of r/c#. the data bus is latched in the rising edge of we#. the program operation, once initiated, will be com- pleted, within 20 s. see figure 14 for program operation timing diagram, figure 17 for timing waveforms, and figure 25 for its flowchart. during the program operation, the only valid reads are data# polling an d toggle bit. during the internal program operation, the host is free to perform addi- tional tasks. any commands written during the internal pro- gram operation will be ignored.
18 data sheet 8 mbit firmware hub sst49lf008a ?2006 silicon storage technology, inc. s71161-11-000 3/06 sector-erase operation the sector-erase operation allows the system to erase the device on a sector-by-sector basis. the sector architecture is based on uniform sector size of 4 kbyte. the sector- erase operation is initiated by executing a six-byte com- mand load sequence for softwa re data protection with sector-erase command (30h) and sector address (sa) in the last bus cycle. the internal erase operation begins after the sixth we# pulse. the end-of-erase can be determined using either data# polling or toggle bit methods. see fig- ure 18 for sector-erase timing waveforms. any commands written during the sector-era se operation will be ignored. block-erase operation the block-erase operation allows the system to erase the device in 64 kbyte uniform block size for the sst49lf008a. the block-erase operation is initiated by executing a six-byte command load sequence for soft- ware data protection with block-erase command (50h) and block address. the internal block-erase operation begins after the sixth we# pulse. the end-of-erase can be determined using either data# polling or toggle bit methods. see figure 19 for timing waveforms. any com- mands written during the block-erase operation will be ignored. chip-erase the sst49lf008a device provides a chip-erase opera- tion only in pp mode, which allows the user to erase the entire memory array to the ?1?s state. this is useful when the entire device must be quickly erased. the chip-erase operation is initiated by executing a six- byte software data protection command sequence with chip-erase command (10h) with address 5555h in the last byte sequence. the internal erase operation begins with the rising edge of the sixth we#. during the internal erase operation, the only valid read is toggle bit or data# polling. see table 9 for the command sequence, figure 20 for tim- ing diagram, and figure 28 for the flowchart. any com- mands written during the chip-erase operation will be ignored. write operation status detection the sst49lf008a device provides two software means to detect the completion of a write (program or erase) cycle, in order to optimize the system write cycle time. the software detection includes tw o status bits: data# polling (dq 7 ) and toggle bit (dq 6 ). the end-of-write detection mode is enabled after the rising edge of we# which ini- tiates the internal program or erase operation. the actual completion of the nonvolatile write is asynchro- nous with the system; therefore, either a data# polling or tog- gle bit read may be simultaneous with the completion of the write cycle. if this occurs, the system may possibly get an erroneous result, i.e., valid data may appear to conflict with either dq 7 or dq 6 . in order to prevent spurious rejection, if an erroneous result occurs, the software routine should include a loop to read the accessed location an additional two (2) times. if both reads are valid, then the device has completed the write cycle, otherwise the rejection is valid. data# polling (dq 7 ) when the sst49lf008a device is in the internal program operation, any attempt to read dq 7 will produce the com- plement of the true data. once the program operation is completed, dq 7 will produce true data. note that even though dq 7 may have valid data immediately following the completion of an internal write operation, the remaining data outputs may still be invalid: valid data on the entire data bus will appear in subsequent successive read cycles after an interval of 1 s. during internal erase opera- tion, any attempt to read dq 7 will produce a ?0?. once the internal erase operation is completed, dq 7 will produce a ?1?. the data# polling is valid after the rising edge of fourth we# pulse for program operation. for sector- or chip- erase, the data# polling is valid after the rising edge of sixth we# pulse. see figure 15 for data# polling timing diagram and figure 26 for a flowchart. proper status will not be given using data# polling if the address is in the invalid range. toggle bit (dq 6 ) during the internal program or erase operation, any con- secutive attempts to read dq 6 will produce alternating ?0?s and ?1?s, i.e., toggling between 0 and 1. when the internal program or erase operation is completed, the toggling will stop. the device is then ready for the next operation. the toggle bit is valid after the rising edge of fourth we# pulse for program operation. for sector-, block- or chip-erase, the toggle bit is valid after the rising edge of sixth we# pulse. see figure 16 for toggle bit timing diagram and fig- ure 26 for a flowchart.
data sheet 8 mbit firmware hub sst49lf008a 19 ?2006 silicon storage technology, inc. s71161-11-000 3/06 data protection the sst49lf008a device provides both hardware and software features to protect nonvolatile data from inadvert- ent writes. hardware data protection noise/glitch protection: a we# pulse of less than 5 ns will not initiate a write cycle. v dd power up/down detection: the write operation is inhibited when v dd is less than 1.5v. write inhibit mode: forcing oe# low, we# high will inhibit the write operation. this prevents inadvertent writes during power-up or power-down. software data protection (sdp) sst49lf008a provides the jedec approved software data protection scheme for all data alteration operation, i.e., program and erase. any program operation requires the inclusion of a series of three-byte sequences. the three-byte load sequence is used to initiate the program operation, providing optimal protection from inadvertent write operations, e.g., during the system power-up or power-down. any erase operation requires the inclusion of a six-byte load sequence. the sst49lf008a device is shipped with the software data protection permanently enabled. see table 9 for the specific software command codes. during sdp command sequence, invalid com- mands will abort the device to read mode, within t rc. table 8: operation modes selection (pp mode) mode rst# oe# we# dq address read v ih v il v ih d out a in program v ih v ih v il d in a in erase v ih v ih v il x 1 sector or block address, xxh for chip-erase reset v il x x high z x write inhibit v ih v il x high z/d out x x xv ih high z/d out x product identification v ih v il v ih manufacturer?s id (bfh) device id 2 a 18 -a 1 =v il , a 0 =v il a 18 -a 1 =v il , a 0 = v ih t8.6 1161 1. x can be v il or v ih , but no other value. 2. device id = 5ah for sst49lf008a
20 data sheet 8 mbit firmware hub sst49lf008a ?2006 silicon storage technology, inc. s71161-11-000 3/06 software comm and sequence table 9: software command sequence command sequence 1st 1 write cycle 1. fwh mode uses consecutive write cycles to complete a command sequence; pp mode uses consecutiv e bus cycles to complete a command sequence. 2nd 1 write cycle 3rd 1 write cycle 4th 1 write cycle 5th 1 write cycle 6th 1 write cycle addr 2 2. address format a 14 -a 0 (hex), addresses a 21 -a 15 can be v il or v ih , but no other value, for the command sequence in pp mode. data addr 2 data addr 2 data addr 2 data addr 2 data addr 2 data byte-program 5555h aah 2aaah 55h 5555h a0h ba 3 3. ba = program byte address data sector-erase 5555h aah 2aaah 55h 5555h 80h 5555h aah 2aaah 55h sa x 4 4. sa x for sector-erase address 30h block-erase 5555h aah 2aaah 55h 5555h 80h 5555h aah 2aaah 55h ba x 5 5. ba x for block-erase address 50h chip-erase 6 6. chip-erase is supported in pp mode only 5555h aah 2aaah 55h 5555h 80h 5555h aah 2aaah 55h 5555h 10h software id entry 7,8 7. sst manufacturer?s id = bfh, is read with a 0 =0, with a 19 -a 1 = 0; 49lf008a device id = 5ah, is read with a 0 = 1. 8. the device does not remain in software product id mode if powered down. 5555h aah 2aaah 55h 5555h 90h software id exit 9 9. both software id exit operations are equivalent. xxh f0h software id exit 9 5555h aah 2aaah 55h 5555h f0h t9.6 1161
data sheet 8 mbit firmware hub sst49lf008a 21 ?2006 silicon storage technology, inc. s71161-11-000 3/06 electrical specifications the ac and dc specifications for the fwh interface signals (fwh[3:0], clk, fwh4, and rst#) as defined in section 4.2.2 of the pci local bus specification, rev. 2.1 . refer to table 10 for the dc voltage and current specifications. refer to the tables on pages 23 through 27 for the ac timing specifications for clock, read/write, and reset operations. absolute maximum stress ratings (applied conditions greater than t hose listed under ?absolute maximum stress ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these conditions or conditions greater t han those defined in the operational sections of this data sheet is not implied. exposu re to absolute maximum stress rating co nditions may affect device reliability.) temperature under bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55c to +125c storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65c to +150c d. c. voltage on any pin to ground potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0 .5v to v dd +0.5v transient voltage (<20 ns) on any pin to ground potential 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -2.0v to v dd +2.0v 1. do not violate processor or chip set limitations on the init# pin. package power dissipation capability (t a =25c) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0w surface mount solder reflow temperature 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260c for 10 seconds 2. excluding certain with-pb 32-plcc units, all packages are 260 c capable in both non-pb and with-pb solder versions. certain with-pb 32-plcc package types are capable of 240 c for 10 seconds; please consult the factory for the latest information. output short circuit current 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 ma 3. outputs shorted for no more than one second. no more than one output shorted at a time. this note applies to non-pci outputs. o perating r ange range ambient temp v dd commercial 0c to +85c 3.0-3.6v ac c onditions of t est 1 1. fwh interface signals use pci load test conditions input rise/fall time . . . . . . . . . . . . . . . 3 ns output load . . . . . . . . . . . . . . . . . . . . . c l = 30 pf see figures 23 and 24
22 data sheet 8 mbit firmware hub sst49lf008a ?2006 silicon storage technology, inc. s71161-11-000 3/06 dc characteristics table 10: dc operating characteristics (all interfaces) symbol parameter limits test conditions 1 1. test conditions apply to pp mode. min max units i dd active v dd current lclk (fwh mode) and address input (pp mode) =v ilt /v iht at f=33 mhz ( fwh mode ) or 1/ trc min ( pp mode ) all other inputs=v il or v ih read 12 ma all outputs = open, v dd =v dd max write 2 2. i dd active while erase or program is in progress. 24 ma see note 3 3. for pp mode: oe# = we# = v ih; for fwh mode: f = 1/t rc min, lframe# = v ih, ce# = v il. i sb standby v dd current (fwh interface) 100 a lclk (fwh mode) and address input (pp mode) =v ilt /v iht at f=33 mhz ( fwh mode ) or 1/ trc min ( pp mode ) lframe#=0.9 v dd , f=33 mhz, ce#=0.9 v dd , v dd =v dd max, all other inputs 0.9 v dd or 0.1 v dd i ry 4 4. the device is in ready mode w hen no activity is on the fwh bus. ready mode v dd current (fwh interface) 10 ma lclk (fwh mode) and address input (pp mode) =v ilt /v iht at f=33 mhz ( fwh mode ) or 1/ trc min ( pp mode ) lframe#=v il , f=33 mhz, v dd =v dd max all other inputs 0.9 v dd or 0.1 v dd i i input current for ic, id [3:0] pins 200 a v in =gnd to v dd , v dd =v dd max i li input leakage current 1 a v in =gnd to v dd , v dd =v dd max i lo output leakage current 1 a v out =gnd to v dd , v dd =v dd max v ihi 5 5. do not violate processor or chipse t specification regarding init# voltage. init# input high voltage 1.0 v dd +0.5 v v dd =v dd max v ili 5 init# input low voltage -0.5 0.4 v v dd =v dd min v il input low voltage -0.5 0.3 v dd vv dd =v dd min v ih input high voltage 0.5 v dd v dd +0.5 v v dd =v dd max v ol output low voltage 0.1 v dd vi ol =1500a, v dd =v dd min v oh output high voltage 0.9 v dd vi oh =-500 a, v dd =v dd min t10.10 1161
data sheet 8 mbit firmware hub sst49lf008a 23 ?2006 silicon storage technology, inc. s71161-11-000 3/06 figure 8: clk waveform table 11: recommended system power-up timings symbol parameter minimum units t pu-read 1 power-up to read operation 100 s t pu-write 1 power-up to write operation 100 s t11.2 1161 1. this parameter is measured only for init ial qualification and after a design or proc ess change that could affect this paramet er table 12: pin impedance (v dd =3.3v, t a =25 c, f=1 mhz, other pins open) parameter description test condition maximum c i/o 1 1. this parameter is measured only for init ial qualification and after a design or proc ess change that could affect this paramet er. i/o pin capacitance v i/o = 0v 12 pf c in 1 input capacitance v in = 0v 12 pf l pin 2 2. refer to pci spec. pin inductance 20 nh t12.4 1161 table 13: reliability characteristics symbol parameter minimum spec ification units test method n end 1 1. this parameter is measured only for init ial qualification and after a design or proc ess change that could affect this paramet er. endurance 10,000 cycles jedec standard a117 t dr 1 data retention 100 years jedec standard a103 i lt h 1 latch up 100 + i dd ma jedec standard 78 t13.3 1161 table 14: clock timing parameters symbol parameter min max units t cyc clk cycle time 30 ns t high clk high time 11 ns t low clk low time 11 ns - clk slew rate (peak-to-peak) 1 4 v/ns - rst# or init# slew rate 50 mv/ns t14.1 1161 1161 f11.0 0.4 v dd p-to-p (minimum) t cyc t high t low 0.4 v dd 0.3 v dd 0.6 v dd 0.2 v dd 0.5 v dd
24 data sheet 8 mbit firmware hub sst49lf008a ?2006 silicon storage technology, inc. s71161-11-000 3/06 ac characteristics (fwh mode) table 15: read/write cycle timing parameters, v dd =3.0-3.6v (fwh mode) symbol parameter min max units t cyc clock cycle time 30 ns t su data set up time to clock rising 7 ns t dh clock rising to data hold time 0 ns t val 1 1. minimum and maximum times have different loads. see pci spec. clock rising to data valid 2 11 ns t bp byte programming time 20 s t se sector-erase time 25 ms t be block-erase time 25 ms t sce chip-erase time 100 ms t on clock rising to active (float to active delay) 2 ns t off clock rising to inactive (active to float delay) 28 ns t15.3 1161 table 16: ac input/output specifications, v dd =3.0-3.6v (fwh mode) symbol parameter limits test conditions min max units i oh (ac) switching current high -12 v dd -17.1(v dd -v out ) equation c 1 1. see pci spec. ma ma 0 < v out 0.3v dd 0.3v dd < v out < 0.9v dd 0.7v dd < v out v out 0.6v dd 0.6v dd > v out > 0.1v dd 0.18v dd > v out > 0 (test point) 38 v dd ma v out =0.18v dd i cl low clamp current -25+(v in +1)/0.015 ma -3 < v in -1 i ch high clamp current 25+(v in -v dd -1)/0.015 ma v dd +4 > v in v dd +1 slewr 2 2. pci specification output load is used. output rise slew rate 1 4 v/ns 0.2v dd -0.6v dd load slewf 2 output fall slew rate 1 4 v/ns 0.6v dd -0.2v dd load t16.3 1161 table 17: reset timi ng parameters, v dd =3.0-3.6v (fwh mode) symbol parameter min max units t prst v dd stable to reset low 1 ms t krst clock stable to reset low 100 s t rstp rst# pulse width 100 ns t rstf rst# low to output float 48 ns t rst 1 1. there will be a latency of t rste if a reset procedure is performed during a program or erase operation. rst# high to fwh4 low 1 s t rste rst# low to reset during sector-/block-erase or program 10 s t17.5 1161
data sheet 8 mbit firmware hub sst49lf008a 25 ?2006 silicon storage technology, inc. s71161-11-000 3/06 figure 9: reset timing diagram figure 10: output timing parameters clk v dd rst#/init# fwh4 fwh[3:0] 1161 f12.0 t prst t krst t rstp t rstf t rste sector-/block-erase or program operation aborted t rst t val v test v tl v th t off t on 1161 f13.0 clk fwh [3:0] (valid output data) fwh [3:0] (float output data)
26 data sheet 8 mbit firmware hub sst49lf008a ?2006 silicon storage technology, inc. s71161-11-000 3/06 figure 11: input timing parameters table 18: interface measurement condition parameters symbol value units v th 1 1. the input test environment is done with 0.1 v dd of overdrive over v ih and v il . timing parameters must be met with no more overdrive than this. v max specified the maximum peak-to-peak waveform allowed for measuring input timing. production testing may us e different voltage values, but must correlate results back to these parameters. 0.6 v dd v v tl 1 0.2 v dd v v test 0.4 v dd v v max 1 0.4 v dd v input signal edge rate 1 v/ns t18.3 1161 t su t dh inputs valid 1161 f14.0 clk fwh [3:0] (valid input data) v test v tl v max v th
data sheet 8 mbit firmware hub sst49lf008a 27 ?2006 silicon storage technology, inc. s71161-11-000 3/06 ac characteristics (pp mode) table 19: read cycle timing parameters, v dd =3.0-3.6v (pp mode) symbol parameter min max units t rc read cycle time 270 ns t rst rst# high to row address setup 1 s t as r/c# address set-up time 45 ns t ah r/c# address hold time 45 ns t aa address access time 120 ns t oe output enable access time 60 ns t olz oe# low to active output 0 ns t ohz oe# high to high-z output 35 ns t oh output hold from address change 0 ns t19.2 1161 table 20: program/erase cycle timing parameters, v dd =3.0-3.6v (pp mode) symbol parameter min max units t rst rst# high to row address setup 1 s t as r/c# address setup time 50 ns t ah r/c# address hold time 50 ns t cwh r/c# to write enable high time 50 ns t oes oe# high setup time 20 ns t oeh oe# high hold time 20 ns t oep oe# to data# polling delay 40 ns t oet oe# to toggle bit delay 40 ns t wp we# pulse width 100 ns t wph we# pulse width high 100 ns t ds data setup time 50 ns t dh data hold time 5 ns t ida software id access and exit time 150 ns t bp byte programming time 20 s t se sector-erase time 25 ms t be block-erase time 25 ms t sce chip-erase time 100 ms t20.2 1161 table 21: reset timi ng parameters, v dd =3.0-3.6v (pp mode) symbol parameter min max units t prst v dd stable to reset low 1 ms t rstp rst# pulse width 100 ns t rstf rst# low to output float 48 ns t rst 1 1. there will be a reset latency of t rste or t rstc if a reset procedure is performed during a program or erase operation. rst# high to row address setup 1 s t rste rst# low to reset during sector-/block-erase or program 10 s t rstc rst# low to reset during chip-erase 50 s t21.1 1161
28 data sheet 8 mbit firmware hub sst49lf008a ?2006 silicon storage technology, inc. s71161-11-000 3/06 figure 12: reset timing diagram (pp mode) figure 13: read cycle timing diagram (pp mode) v dd rst# addresses r/c# dq 7-0 1161 f15.0 t prst t rstp t rstf t rste row address sector-/block-erase or program operation aborted t rst t rstc chip-erase aborted 1161 f16.0 column address data valid high-z row address column address row address rst# addresses r/c# v ih high-z t rst t rc t as t ah t ah t aa t oe t olz t ohz t oh t as we# oe# dq 7-0 t rstp
data sheet 8 mbit firmware hub sst49lf008a 29 ?2006 silicon storage technology, inc. s71161-11-000 3/06 figure 14: write cycle timing diagram (pp mode) figure 15: data# polling timing diagram (pp mode) 1161 f17.0 column address row address data valid rst# addresses r/c# t rst t as t ah t cwh t wp t wph t oeh t dh t ds t ah t as we# oe# dq 7-0 t oes t rstp 1161 f18.0 addresses r/c# t oep row column we# oe# dq 7 d# d d# d
30 data sheet 8 mbit firmware hub sst49lf008a ?2006 silicon storage technology, inc. s71161-11-000 3/06 figure 16: toggle bit timing diagram (pp mode) figure 17: byte-program timing diagram (pp mode) 1161 f19.0 addresses r/c# t oet row column we# oe# dq 6 d d 1161 f20.0 t wp t wph t bp four-byte code for byte-program 5555 2aaa 5555 ba sb0 ba = byte-program address sb1 sb2 sb3 internal program starts we# addresses r/c# oe# data 55 aa a0 dq 7-0
data sheet 8 mbit firmware hub sst49lf008a 31 ?2006 silicon storage technology, inc. s71161-11-000 3/06 figure 18: sector-erase timing diagram (pp mode) figure 19: block-erase timing diagram (pp mode) 1161 f21.0 t wp t wph t se six-byte code for sector-erase operation 5555 2aaa 5555 5555 2aaa sa x sb0 sa x = sector address sb1 sb2 sb3 sb4 sb5 internal erasure starts we# addresses r/c# oe# 55 aa 55 aa 80 30 dq 7-0 1161 f22.0 t wp t wph t be six-byte code for block-erase operation 5555 2aaa 5555 5555 2aaa ba x sb0 ba x = block address sb1 sb2 sb3 sb4 sb5 internal erasure starts we# addresses r/c# oe# 55 aa 55 aa 80 50 dq 7-0
32 data sheet 8 mbit firmware hub sst49lf008a ?2006 silicon storage technology, inc. s71161-11-000 3/06 figure 20: chip-erase timing diagram (pp mode) figure 21: software id entry and read (pp mode) 1161 f23.0 t wp t wph t sce six-byte code for chip-erase operation 5555 2aaa 5555 5555 2aaa 5555 sb0 sb1 sb2 sb3 sb4 sb5 internal erasure starts we# addresses r/c# oe# 55 aa 55 aa 80 10 dq 7-0 1161 f24.2 addresses t ida dq 7-0 we# sw0 device id = 5ah for sst49lf008a sw1 sw2 5555 2aaa 5555 0000 0001 oe# r/c# three-byte sequence for software id entry t wp t wph t aa bf device id 55 aa 90
data sheet 8 mbit firmware hub sst49lf008a 33 ?2006 silicon storage technology, inc. s71161-11-000 3/06 figure 22: software id exit and reset (pp mode) figure 23: ac input/output reference waveforms (pp mode) figure 24: a test load example (pp mode) 1161 f25.0 addresses dq 7-0 t ida t wp t wph we# sw0 sw1 sw2 5555 2aaa 5555 three-byte sequence for software id exit and reset oe# r/c# aa 55 f0 1161 f26.0 reference points output input v it v iht v ilt v ot ac test inputs are driven at v iht (0.9 v dd ) for a logic ?1? and v ilt (0.1 v dd ) for a logic ?0?. measurement reference points for inputs and outputs are v it (0.5 v dd ) and v ot (0.5 v dd ). input rise and fall times (10% ? 90%) are <5 ns. note: v it - v input te s t v ot - v output te s t v iht - v input high test v ilt - v input low test 1161 f27.0 to tester to dut c l
34 data sheet 8 mbit firmware hub sst49lf008a ?2006 silicon storage technology, inc. s71161-11-000 3/06 figure 25: byte-program algorithm 1161 f28.0 start write data: aah address: 5555h write data: 55h address: 2aaah write data: a0h address: 5555h load byte address/byte data wait for end of program (t bp , data# polling bit, or toggle bit operation) program completed
data sheet 8 mbit firmware hub sst49lf008a 35 ?2006 silicon storage technology, inc. s71161-11-000 3/06 figure 26: wait options 1161 f29.0 wait t bp , t sce, t be or t se byte- program/erase initiated internal timer toggle bit ye s ye s no no program/erase completed does dq 6 match? read same byte data# polling program/erase completed program/erase completed read byte is dq 7 = true data? read dq 7 byte- program/erase initiated byte- program/erase initiated
36 data sheet 8 mbit firmware hub sst49lf008a ?2006 silicon storage technology, inc. s71161-11-000 3/06 figure 27: software product command flowcharts 1161 f30.0 write data: aah address: 5555h software product id entry command sequence write data: 55h address: 2aaah write data: 90h address: 5555h wait t ida read software id write data: aah address: 5555h software product id exit & reset command sequence write data: 55h address: 2aaah write data: f0h address: 5555h write data: f0h address: xxh return to normal operation wait t ida wait t ida return to normal operation
data sheet 8 mbit firmware hub sst49lf008a 37 ?2006 silicon storage technology, inc. s71161-11-000 3/06 figure 28: erase command sequence 1161 f31.0 write data: aah address: 5555h chip-erase command sequence write data: 55h address: 2aaah write data: 80h address: 5555h write data: 55h address: 2aaah write data: 10h address: 5555h write data: aah address: 5555h wait options chip erased to ffh write data: aah address: 5555h sector-erase command sequence write data: 55h address: 2aaah write data: 80h address: 5555h write data: 55h address: 2aaah write data: 30h address: sa x write data: aah address: 5555h wait options sector erased to ffh write data: aah address: 5555h block-erase command sequence write data: 55h address: 2aaah write data: 80h address: 5555h write data: 55h address: 2aaah write data: 50h address: ba x write data: aah address: 5555h wait options block erased to ffh
38 data sheet 8 mbit firmware hub sst49lf008a ?2006 silicon storage technology, inc. s71161-11-000 3/06 product ordering information valid combinations for sst49lf008a sst49lf008a-33-4c-whe sst49lf008a-33-4c-nhe SST49LF008A-33-4C-EIE note: valid combinations are those products in mass producti on or will be in mass production. consult your sst sales representative to confirm availability of valid combinat ions and to determine availability of new combinations. device speed suffix1 suffix2 suffix3 sst49 l f00x a - xxx -x x -x x x environmental attribute e 1 = non-pb package modifier h = 32 leads i = 40 leads package type n = plcc w = tsop (type 1, die up, 8mm x 14mm) e = tsop (type 1, die up, 10mm x 20mm) operating temperature c = commercial = 0c to +85c minimum endurance 4 = 10,000 cycles serial access clock frequency 33 = 33 mhz version a = second version device density 008 = 8 mbit voltage range l = 3.0-3.6v product series 49 = firmware hub fo r intel 8xx chipsets 1. environmental suffix ?e? denotes non-pb solder. sst non-pb solder devices are ?rohs compliant?.
data sheet 8 mbit firmware hub sst49lf008a 39 ?2006 silicon storage technology, inc. s71161-11-000 3/06 packaging diagrams figure 29: 32-lead plastic lead chip carrier (plcc) sst package code: nh .040 .030 .021 .013 .530 .490 .095 .075 .140 .125 .032 .026 .032 .026 .029 .023 .453 .447 .553 .547 .595 .585 .495 .485 .112 .106 .042 .048 .048 .042 .015 min. top view side view bottom view 1 232 .400 bsc 32-plcc-nh-3 note: 1. complies with jedec publication 95 ms-016 ae dimensions, although some dimensions may be more stringent. 2. all linear dimensions are in inches (max/min). 3. dimensions do not include mold flash. maximum allowable mold flash is .008 inches. 4. coplanarity: 4 mils. .050 bsc .050 bsc optional pin #1 identifier .020 r. max. r. x 30?
40 data sheet 8 mbit firmware hub sst49lf008a ?2006 silicon storage technology, inc. s71161-11-000 3/06 figure 30: 32-lead thin small outline package (tsop) 8mm x 14mm sst package code: wh 32-tsop-wh-7 note: 1. complies with jedec publication 95 mo-142 ba dimensions, although some dimensions may be more stringent. 2. all linear dimensions are in millimeters (max/min). 3. coplanarity: 0.1 mm 4. maximum allowable mold flash is 0.15 mm at the package ends, and 0.25 mm between leads. 1.20 max. 1mm pin # 1 identifier 12.50 12.30 14.20 13.80 0.70 0.50 8.10 7.90 0.27 0.17 0. 50 bsc 1.05 0.95 0.15 0.05 0.70 0.50 0?- 5? detail
data sheet 8 mbit firmware hub sst49lf008a 41 ?2006 silicon storage technology, inc. s71161-11-000 3/06 figure 31: 40-lead thin small outline package (tsop) 10mm x 20mm sst package code: ei 18.50 18.30 20.20 19.80 0.70 0.50 10.10 9.90 0.27 0.17 1.05 0.95 0.15 0.05 0.70 0.50 40-tsop-ei-7 note: 1. complies with jedec publication 95 mo-142 cd dimensions, although some dimensions may be more stringent. 2. all linear dimensions are in millimeters (max/min). 3. coplanarity: 0.1 mm 4. maximum allowable mold flash is 0.15 mm at the package ends, and 0.25 mm between leads. pin # 1 identifier 0.50 bsc 1.20 max. 0?- 5? detail 1mm
42 data sheet 8 mbit firmware hub sst49lf008a ?2006 silicon storage technology, inc. s71161-11-000 3/06 table 22: revision history revision draft changes date 06 ? 2002 data book ? changed transient voltage from -1.0v to v dd +1.0v to -2.0v to v dd +2.0v to match intel fwh spec per ibm requirement. ? added footnote for transient voltage. ? updated footnote for output short circuit current. ? updated data# polling description ? corrected the values in table 5 on page 15: general purpose inputs register ? added note to table 10 on page 22: dc operating characteristics july 2001 07 ? added 40-lead tsop for sst49lf008a only ? corrected the i dd test conditions in table 10 on page 22 june 2003 08 ? 2004 data book ? updated document status to data sheet dec 2003 09 ? removed 2 mbit and 3 mbit devices - refer to eol product data sheet s71161(01) oct 2004 10 ? removed 32-plcc (nh/nhe) package and associated mpns for the 4 mbit device refer to eol product data sheet s71161(03). ? clarified the solder temperature profile under ?absolute maximum stress ratings? on page 21 nov 2004 11 ? removed 4 mbit wh/whe device - refer to eol product data sheet s71161(03) ? added statement that non-pb devices are rohs compliant to features section ? updated surface mount solder reflow temperature information ? removed leaded part numbers ? applied new formatting mar 2006 silicon storage technology, inc. ? 1171 sonora court ? sunnyvale, ca 94086 ? telephone 408-735-9110 ? fax 408-735-9036 www.superflash.com or www.sst.com

▲Up To Search▲

Price & Availability of SST49LF008A-33-4C-EIE

	To Download SST49LF008A-33-4C-EIE Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .